Digital Computer Arithmetic Datapath Design Using Verilog HDL, James E. Stine, Kluwer Academic Publishers, Boston, 2004, ISBN 1-4020-7710-6. Hardcover, pp 180, plus XI

ion, 7Additionblock carry lookahead generator (BCLG), 36carry lookahead adder (CLA), 34carry lookahead generator (CLG), 34carry propagate addition (CPA), 29carry select adder (CSEA), 43carry skip adder (CKSA), 40generate, 29half adders, 28prefix adder, 49propagate, 29reduced full adder (RFA), 38ripple carry adder (RCA), 30ripple carry adder/subtractor (RCAS), 31Baseline units, 5Booth decoder, 91Booth selector, 91Booth’s algorithm, 86Brent-Kung adder, 51Canonical SD representation, 85Carry chain, 29Carry propagate addition, 57Carry save example, 58Column compression multipler, 66Control logic, 4Convergence, 163Counter, 29Dadda’s reduction, 65Datapath design, 3DesignWare example, 24Desing process, 9Device under test (DUT), 18DEVS, 22Digit recurrence, 104Divide and conquer, 15Dividend, 114Divisionconstant comparison, 107continuity, 106overlapping stages, 124quotient overlap, 107radix 16 division, 122radix 2 division, 112radix 4 division with carry-save adder, 119radix 4 division, 115selection interval, 106Divisor, 114Elementary functionbipartite table methods, 141SBTM, 142STAM, 143constant approximation, 133CORDIC, 147linear approximation, 136piecewise constant approximation, 134table lookup, 131Error analysis, 129Fractional multiplication, 92Gajski-Kuhn Y chart, 8Golden file, 19Goldschmidt’s Division example, 167Goldschmidt’s division, 166Hierarchy, 8Logarithmic shifter, 152Maple, 137Minimax, 137Modified full adder (MFA), 60Most Significant Digit First (MSDF), 108Multiplexor, 43Multiplicand, 56Multiplication matrix, 56Multiplicationcarry save array Booth multiplier, 88radix-4 modified Booth multiplier, 89signed modified radix-4 modified Boothmultiplier, 91steps, 56tree multiplier, 61 180DIGITAL COMPUTER ARITHMETIC DATAPATH DESIGN Dadda multiplier, 65Reduced Area (RA) multiplier, 68Wallace multiplier, 61truncated multiplication, 72constant correction truncated multiplier(CCT), 72hybrid correction truncated (VCT) multiplier,76variable correction truncated (VCT)multiplier, 73two’s complement multiplication, 78unsigned binary multiplication, 56Multiplicative divide, 161division by convergence, 166Newton-Raphson, 161Multiplier, 56Negating modified full adder (NMFA), 81Newton-Raphson Division example, 162Objective, 2On-the-fly-conversion, 108Parallel multiplier, 55Parallel prefix addition, 47Partial product reduction, 63Partial remainder, 115Pentium bug, 17PLA, 107Product, 56QST, 104Quadratic convergence, 161Quotient digit selection, 105Quotient, 103Recurrence relation, 104Reduced full adder (RFA), 73Redundant adder, 118Round to nearest-even (RNE), 138Rounding, 138RTL level, 2Serial multiplier, 55Siged Digit (SD) numbers, 82SRT, 113Symmetry for SBTM and STAM, 145Time borrowing, 4Unit in the last position (ulp), 81Verilogbitwise operator, 87concatenation, 19delay-based timing, 23DesignWare, 24event-based timing, 23full adders, 29IEEE1364-1995, 1IEEE1364-2001, 24IEEE1364.1, 13instantiation, 11intellectual property (IP), 24memory, 14ROM, 15module call, 16module declaration, 16module structure, 15naming methodology, 10nets, 12number readability, 11output format, 21radices, 11registers, 13replication, 21standard output, 21stopping a stimulation, 21test bench design, 19test bench, 18testing methodology, 17testing, 16timing, 22vectors, 14wire naming convention, 25Wallace’s equation, 62Wire naming convention, 25